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» Diagonal routing in high performance microprocessor design
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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 9 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
16 years 2 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
EMSOFT
2005
Springer
15 years 11 months ago
High performance annotation-aware JVM for Java cards
Early applications of smart cards have focused in the area of personal security. Recently, there has been an increasing demand for networked, multi-application cards. In this new ...
Ana Azevedo, Arun Kejariwal, Alexander V. Veidenba...
TVLSI
2010
15 years 9 days ago
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
Hamed F. Dadgour, Kaustav Banerjee
IEEEPACT
2003
IEEE
15 years 11 months ago
Design Trade-Offs in High-Throughput Coherence Controllers
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
Anthony-Trung Nguyen, Josep Torrellas