787 search results - page 66 / 158 » Digital Algebra and Circuits |
PARLE
1987
1987
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
14 years 15 days ago
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
ETS
2009
IEEE
13 years 6 months ago
2009
IEEE
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...