5740 search results - page 1000 / 1148 » Dynamic Distributed BackJumping |
HPCA
2006
IEEE
14 years 10 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
HPCA
2005
IEEE
14 years 10 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
HPCA
2003
IEEE
14 years 10 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
HPCA
2002
IEEE
14 years 10 months ago
2002
IEEE
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
HPCA
2001
IEEE
14 years 10 months ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...