473 search results - page 57 / 95 » Dynamic Memory Design for Low Data-Retention Power |
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
IJRR
2006
13 years 8 months ago
2006
We examine the design, control and performance of the Cobotic Hand Controller, a novel, six-degree-of-freedom, admittance controlled haptic display. A highly geared admittance arch...
TVLSI
2010
13 years 3 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...