130 search results - page 4 / 26 » Dynamically Scheduling VLIW Instructions |
ISCAPDCS
2001
13 years 8 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...