286 search results - page 26 / 58 » Efficient Hardware Architectures for Modular Multiplication ... |
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
CF
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...