24 search results - page 1 / 5 » Efficient Testing of Clock Regenerator Circuits in Scan Desi... |
DAC
1997
ACM
14 years 21 days ago
1997
ACM
DAC
2003
ACM
14 years 1 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
ICCAD
2000
IEEE
14 years 28 days ago
2000
IEEE
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
ITC
1992
IEEE
14 years 17 days ago
1992
IEEE
This paper presents a BIST technique that allows the synchronization of multiple scan chains clocked at different frequencies. The technique is used to improve performance testing...