24 search results - page 2 / 5 » Efficient Testing of Clock Regenerator Circuits in Scan Desi... |
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISLPED
2005
ACM
14 years 4 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
DAC
2005
ACM
14 years 24 days ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
DFT
2000
IEEE
14 years 3 months ago
2000
IEEE
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
IOLTS
2008
IEEE
14 years 5 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...