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DATE
2003
IEEE
131views Hardware» more  DATE 2003»
14 years 3 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 4 months ago
An Organic Computing architecture for visual microprocessors based on Marching Pixels
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
Dietmar Fey, Marcus Komann, Frank Schurz, Andreas ...
DAC
2008
ACM
14 years 11 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 4 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
IWDW
2005
Springer
14 years 3 months ago
Watermarking of 3D Irregular Meshes Based on Wavelet Multiresolution Analysis
In this paper, we propose a robust watermarking method for 3-D triangle surface meshes. Most previous methods based on the wavelet analysis can process only semi-regular meshes. Ou...
Min-Su Kim, Sébastien Valette, Ho-Youl Jung...