29 search results - page 2 / 6 » Energy-recovery CMOS for highly pipelined DSP designs |
TVLSI
2010
13 years 3 months ago
2010
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
ISSS
1995
IEEE
14 years 10 days ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present h...
FPL
2003
Springer
14 years 2 months ago
2003
Springer
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...