146 search results - page 5 / 30 » Enhanced clustered voltage scaling for low power |
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
ISLPED
2004
ACM
14 years 26 days ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
MICRO
2003
IEEE
14 years 21 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...