70 search results - page 5 / 14 » Enhanced leakage reduction Technique by gate replacement |
FPGA
2004
ACM
14 years 26 days ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
NANONET
2009
Springer
14 years 2 months ago
2009
Springer
The Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace traditional FETs in sleep mode circuits, due to its abrupt switching enabled by electro...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...