710 search results - page 8 / 142 » Estimating design time for system circuits |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
DATE
2008
IEEE
13 years 9 months ago
2008
IEEE
In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed realtime systems. Schedulability analysis produces pessimistic uppe...