501 search results - page 27 / 101 » Evaluating CMPs and Their Memory Architecture |
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
EDBT
2010
ACM
13 years 11 months ago
2010
ACM
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controller...
ISCAPDCS
2007
13 years 9 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...