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» Evaluating Run-Time Techniques for Leakage Power Reduction
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ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 1 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 1 months ago
Low power SRAM techniques for handheld products
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
Rabiul Islam, Adam Brand, Dave Lippincott
ICCD
2002
IEEE
137views Hardware» more  ICCD 2002»
14 years 4 months ago
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
Stephanie Augsburger, Borivoje Nikolic
ICPP
2009
IEEE
13 years 5 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
PATMOS
2004
Springer
14 years 28 days ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...