453 search results - page 45 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2004
IEEE
14 years 9 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
RSP
2000
IEEE
14 years 1 months ago
2000
IEEE
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...