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ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
14 years 16 days ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 9 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
RTAS
2002
IEEE
14 years 1 months ago
Experiences in Implementing an Energy-Driven Task Scheduler in RT-Linux
Dynamic voltage scaling (DVS) is being increasingly used for power management in embedded systems. Energy is a scarce resource in embedded real-time systems and energy consumption...
Vishnu Swaminathan, Charles B. Schweizer, Krishnen...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
14 years 2 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber