1256 search results - page 208 / 252 » Experiences with the DEVStone benchmark |
GECCO
2007
Springer
14 years 5 months ago
2007
Springer
This research uses a Design of Experiments (DOE) approach to build a predictive model of the performance of a combinatorial optimization heuristic over a range of heuristic tuning...
PPOPP
2005
ACM
14 years 4 months ago
2005
ACM
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...
GLVLSI
2010
IEEE
14 years 3 months ago
2010
IEEE
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
ISCA
2010
IEEE
14 years 3 months ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
IEEEPACT
2000
IEEE
14 years 3 months ago
2000
IEEE
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...