An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or IDDQ testing. Theoretica...
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...