375 search results - page 11 / 75 » Explicit gate delay model for timing evaluation |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...