375 search results - page 9 / 75 » Explicit gate delay model for timing evaluation |
MOBIMEDIA
2007
13 years 9 months ago
2007
We investigate the performance of the IEEE 802.11e while emphasizing on the end-to-end delay performance. In our MAC delay analysis, we are based on elementary conditional probabi...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...