87 search results - page 4 / 18 » FPGA power reduction using configurable dual-Vdd |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
APCCAS
2006
IEEE
13 years 9 months ago
2006
IEEE
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...