Sciweavers

159 search results - page 6 / 32
» Fast Design Space Exploration Method for Reconfigurable Arch...
Sort
View
CASES
2008
ACM
13 years 9 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
ASPDAC
2005
ACM
116views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A flexible framework for communication evaluation in SoC design
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 7 months ago
Automatic Model Refinement for Fast Architecture Exploration
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...
Junyu Peng, Samar Abdi, Daniel Gajski
CODES
2004
IEEE
13 years 11 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CODES
2003
IEEE
14 years 24 days ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha