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DAC
2004
ACM
14 years 25 days ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 18 days ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
DATE
2010
IEEE
127views Hardware» more  DATE 2010»
14 years 15 days ago
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
— Pattern recognition has many applications in design automation. A generalized pattern recognition algorithm is presented in this paper which can efficiently extract similar pat...
Jason Cong, Hui Huang, Wei Jiang
CDC
2009
IEEE
147views Control Systems» more  CDC 2009»
14 years 3 days ago
A simulation-based method for aggregating Markov chains
— This paper addresses model reduction for a Markov chain on a large state space. A simulation-based framework is introduced to perform state aggregation of the Markov chain base...
Kun Deng, Prashant G. Mehta, Sean P. Meyn
ICCD
2000
IEEE
87views Hardware» more  ICCD 2000»
13 years 11 months ago
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a ...
Subarnarekha Sinha, Sunil P. Khatri, Robert K. Bra...