A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...