160 search results - page 5 / 32 » Fast simulation of VLSI interconnects |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
SAC
1995
ACM
13 years 10 months ago
1995
ACM
A trigger system in High Energy Physics Experiments (HEPE) has to decide, in few µs, if the data related to a nuclear event have to be stored or not. Normally, these data, are co...
VTS
2002
IEEE
14 years 19 hour ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...