730 search results - page 101 / 146 » Faster dimension reduction |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
ISLPED
2006
ACM
14 years 2 months ago
2006
ACM
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and ...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...