372 search results - page 61 / 75 » Fault simulation on reconfigurable hardware |
ISQED
2002
IEEE
14 years 25 days ago
2002
IEEE
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Using additional store-checkpoinsts (SCPs) and compare-checkpoints (CCPs), we present an adaptive checkpointing for double modular redundancy (DMR) in this paper. The proposed app...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
DATE
1999
IEEE
14 years 7 days ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...