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» Fault tolerant nanoelectronic processor architectures
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DSN
2003
IEEE
14 years 23 days ago
An Algorithm for Automatically Obtaining Distributed and Fault-Tolerant Static Schedules
Our goal is to automatically obtain a distributed and fault-tolerant embedded system: distributed because the system must run on a distributed architecture; fault-tolerant because...
Alain Girault, Hamoudi Kalla, Mihaela Sighireanu, ...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 2 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
ISCA
2011
IEEE
270views Hardware» more  ISCA 2011»
12 years 11 months ago
Sampling + DMR: practical and low-overhead permanent fault detection
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Ve...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
HPCA
2007
IEEE
14 years 7 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...