15 search results - page 1 / 3 » Fault-Simulation Based Design Error Diagnosis for Sequential... |
DAC
1998
ACM
14 years 8 months ago
1998
ACM
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
DFT
2003
IEEE
14 years 22 days ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design ...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...