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» FinFETs for nanoscale CMOS digital integrated circuits
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DATE
2010
IEEE
170views Hardware» more  DATE 2010»
14 years 13 days ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
DAC
2006
ACM
14 years 1 months ago
Tomorrow's analog: just dead or just different?
This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big ...
Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien ...
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 4 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
ICCAD
2000
IEEE
171views Hardware» more  ICCAD 2000»
13 years 11 months ago
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...
Michael Pronath, Volker Gloeckel, Helmut E. Graeb
DAC
1994
ACM
13 years 11 months ago
Statistical Estimation of the Switching Activity in Digital Circuits
Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
Michael G. Xakellis, Farid N. Najm