This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang...
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...