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» Finding optimal L1 cache configuration for embedded systems
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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 15 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
CGO
2005
IEEE
14 years 1 months ago
Effective Adaptive Computing Environment Management via Dynamic Optimization
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John
ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
14 years 4 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel
ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
13 years 11 months ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 7 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...