1563 search results - page 13 / 313 » Flexible instruction processors |
HPCA
2006
IEEE
14 years 10 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
DATE
2004
IEEE
14 years 1 months ago
2004
IEEE
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, t...
ASPDAC
1999
ACM
14 years 2 months ago
1999
ACM
Abstract Due to the large variety of di erent embedded processor types, retargetable software development tools, such as compilers and simulators, have received attention recently....