161 search results - page 24 / 33 » Floorplanning with Datapath Optimization |
DATE
2007
IEEE
14 years 5 months ago
2007
IEEE
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
ICCAD
2009
IEEE
13 years 8 months ago
2009
IEEE
Dramatic progress has been made in algorithms for placement and routing over the last 5 years, with improvements in both speed and quality. Combining placement and routing into a ...
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...