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ITC
1992
IEEE
90views Hardware» more  ITC 1992»
14 years 1 months ago
ScanBIST: A Multi-frequency Scan-based BIST Method
This paper presents a BIST technique that allows the synchronization of multiple scan chains clocked at different frequencies. The technique is used to improve performance testing...
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hass...
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
14 years 1 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 6 months ago
Temperature-aware test scheduling for multiprocessor systems-on-chip
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
David R. Bild, Sanchit Misra, Thidapat Chantem, Pr...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
14 years 1 months ago
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
Hao Fang, Chenguang Tong, Xu Cheng
DELTA
2004
IEEE
14 years 24 days ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi