This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...