33 search results - page 4 / 7 » Functionally linear decomposition and synthesis of logic cir... |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
FPL
2005
Springer
14 years 29 days ago
2005
Springer
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...