694 search results - page 11 / 139 » Gate Sizing Using a Statistical Delay Model |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
DAC
1996
ACM
13 years 12 months ago
1996
ACM
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ICCAD
2000
IEEE
14 years 3 days ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...