694 search results - page 18 / 139 » Gate Sizing Using a Statistical Delay Model |
VTS
2003
IEEE
14 years 29 days ago
2003
IEEE
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
DATE
1999
IEEE
14 years 22 hour ago
1999
IEEE
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...
TVLSI
2002
13 years 7 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...