694 search results - page 28 / 139 » Gate Sizing Using a Statistical Delay Model |
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
NCA
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we propose and analyze a methodology for providing statistical guarantees within the diffserv model in a network, that uses static-priority schedulers. We extend th...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
RTSS
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper, we derive a statistical delay guarantee of the generalized Virtual Clock scheduling algorithm. We define the concept of an equivalent fluid and packet source and pr...