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» Gate Sizing Using a Statistical Delay Model
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DATE
2010
IEEE
178views Hardware» more  DATE 2010»
14 years 2 months ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
ACE
2004
224views Education» more  ACE 2004»
13 years 10 months ago
Automating the Estimation of Project Size from Software Design Tools Using Modified Function Points
Final year students in the Bachelor of Computing complete an industry project where they work in teams to build an IT system for an external client. Grading projects in these circ...
Jason Ceddia, Martin Dick
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
14 years 2 months ago
Multilevel routing with antenna avoidance
As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide...
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 2 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 2 months ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....