694 search results - page 9 / 139 » Gate Sizing Using a Statistical Delay Model |
ICCAD
2000
IEEE
14 years 2 days ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
ICCAD
2003
IEEE
14 years 29 days ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...