44 search results - page 7 / 9 » Gate delay calculation considering the crosstalk capacitance... |
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage valu...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...