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ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
14 years 2 months ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
14 years 2 months ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang
CASES
2007
ACM
13 years 12 months ago
An optimistic and conservative register assignment heuristic for chordal graphs
This paper presents a new register assignment heuristic for procedures in SSA Form, whose interference graphs are chordal; the heuristic is called optimistic chordal coloring (OCC...
Philip Brisk, Ajay K. Verma, Paolo Ienne
ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
14 years 4 months ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
14 years 7 days ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...