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CODES
2008
IEEE
14 years 1 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
DAGSTUHL
2006
13 years 8 months ago
Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution
Abstract. Within Self-reconfiguring systems two basic problems arise: on instruction level, reconfigurable instruction sets make program generation and execution inherently difficu...
Rainer Buchty
FPGA
2006
ACM
178views FPGA» more  FPGA 2006»
13 years 10 months ago
Application-specific customization of soft processor microarchitecture
A key advantage of soft processors (processors built on an FPGA programmable fabric) over hard processors is that they can be customized to suit an application program's spec...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ASPDAC
1999
ACM
98views Hardware» more  ASPDAC 1999»
13 years 11 months ago
Generation of Interpretive and Compiled Instruction Set Simulators
Abstract Due to the large variety of di erent embedded processor types, retargetable software development tools, such as compilers and simulators, have received attention recently....
Rainer Leupers, Johann Elste, Birger Landwehr
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
13 years 12 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...