339 search results - page 25 / 68 » Hardware Synthesis for Multi-Dimensional Time |
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FPL
2010
Springer
15 years 1 months ago
2010
Springer
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
130
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ICCAD
2006
IEEE
16 years 22 days ago
2006
IEEE
Abstract— Chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ICs). Many methods of IC ...
129
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ISQED
2007
IEEE
15 years 10 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
130
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ISPD
2000
ACM
15 years 8 months ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
128
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ICCD
2004
IEEE
16 years 22 days ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...