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» Hardware Synthesis from C C Models
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111
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FPL
2007
Springer
80views Hardware» more  FPL 2007»
15 years 10 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 8 months ago
Transformational partitioning for co-design of multiprocessor systems
This paper presents the underlying methodology of Cosmos, an interactive approach for hardware software co-design capable of handling multiprocessor systems and distributed archit...
Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ah...
91
Voted
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 9 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
123
Voted
ICCAD
2002
IEEE
82views Hardware» more  ICCAD 2002»
15 years 9 months ago
Hardware/software partitioning of software binaries
Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent ...
Greg Stitt, Frank Vahid
ICCAD
1996
IEEE
86views Hardware» more  ICCAD 1996»
15 years 8 months ago
Polarized observability don't cares
A new method is presented to compute the exact observability don't cares (ODC) for multilevel combinational circuits. A new mathematical concept, called polarization, is intr...
Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van...