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» Hardware Synthesis from C C Models
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DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 2 months ago
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Simila...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 1 months ago
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
Marco Caldari, Massimo Conti, Massimo Coppola, Ste...
DAC
2006
ACM
14 years 1 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
ISMVL
2003
IEEE
111views Hardware» more  ISMVL 2003»
14 years 1 months ago
Modeling Multi-Valued Circuits in SystemC
The complexity of todays hardware systems steadily increases. Due to this fact new ways of efficiently describing systems are investigated. A very promising approach in this area...
Daniel Große, Görschwin Fey, Rolf Drech...
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...