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CODES
2003
IEEE
14 years 2 months ago
Transaction level modeling: an overview
Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the us...
Lukai Cai, Daniel Gajski
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
14 years 5 months ago
Test-model based hierarchical DFT synthesis
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Curre...
Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, ...
DAC
2003
ACM
14 years 10 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav
DT
2006
180views more  DT 2006»
13 years 9 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 2 months ago
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover...
Yves Vanderperren, Wim Dehaene